Physical Design Engineer

Headhunter: Intellectual Capital Resources

Produktion Halbleiter

8040 Zürich, Zurich - Schweiz

Senior Fachkraft / Projektleiter

Experteer Overview

In this role you drive end-to-end ASIC implementation, from synthesis to signoff, collaborating with front-end, verification and system teams to tackle timing and physical challenges on advanced nodes. You influence design methodologies, improve flows, and support tapeouts and post-implementation analysis. The role blends hands-on RTL-to-GDSII work with automation, low-power strategies, and SoC integration to deliver high-performance silicon.

Verantwortungsbereiche

Drive ASIC implementation from synthesis through place & route, timing closure and final signoff
Refine timing, power and physical constraints to meet performance targets
Perform static timing analysis and resolve complex implementation challenges
Collaborate with RTL and verification teams to optimize designs for physical implementation
Support low-power implementation strategies and modern SoC integration activities
Enhance automation and methodology through scripting and flow development
Contribute to successful tapeouts and post-implementation analysis

Zentrale Anforderungen

Proven experience in ASIC Physical Design and back-end implementation
Strong understanding of synthesis, place & route, clock tree synthesis, STA and timing closure
Experience owning or contributing to RTL-to-GDSII flow
Knowledge of modern SoC architectures and integration flows
Familiarity with Verilog/SystemVerilog and understanding interaction between RTL and physical implementation
Hands-on experience with industry-standard EDA tools (Synopsys, Cadence or Siemens)
Scripting experience using Python, Tcl or similar languages
Ability to debug and solve complex implementation and timing issues

ASIC Physical Design and back-end implementation Synthesis, place & route (P&R)Clock Tree Synthesis (CTS)Static Timing Analysis (STA)RTL-to-GDSII flow SoC architectures and integration flows

Stellenbeschreibung

In this role you drive end-to-end ASIC implementation, from synthesis to signoff, collaborating with front-end, verification and system team…

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